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Hot-carrier evaluation of a zero-cost transistor developed via process optimization in an embedded non-volatile memory CMOS technology

Abstract : A new transistor architecture is developed by reusing already existing fabrication process bricks in an embedded nonvolatile memory (eNVM) sub-40 nm CMOS technology, resulting in a middle-voltage zero-cost transistor, ideal for lowcost products. TCAD simulations are undertaken to confirm the feasibility of the process optimization and predict the transistor performance. The new transistor is fabricated then electrically characterized. The new device shows good analogue performances for no cost added. A hot-carrier injection (HCI) degradation evaluation is performed and confirms the reliability of the device. .
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https://hal.archives-ouvertes.fr/hal-03500203
Contributor : Hassan Aziza Connect in order to contact the contributor
Submitted on : Thursday, January 6, 2022 - 5:09:29 PM
Last modification on : Sunday, May 1, 2022 - 3:15:02 AM
Long-term archiving on: : Thursday, April 7, 2022 - 6:17:44 PM

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P. Devoge, Hassen Aziza, P. Lorenzini, F. Julien, A. Marzaki, et al.. Hot-carrier evaluation of a zero-cost transistor developed via process optimization in an embedded non-volatile memory CMOS technology. Microelectronics Reliability, Elsevier, 2021, 126, pp.114265. ⟨10.1016/j.microrel.2021.114265⟩. ⟨hal-03500203⟩

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